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| FAN5182 -- Adjustable Output 1-, 2-, or 3-Phase Synchronous Buck Controller March 2008 FAN5182 -- Adjustable Output, 1-, 2-, or 3-Phase Synchronous Buck Controller Features Selectable 1-, 2-, or 3-Phase Operation at up to 1MHz per Phase Accuracy: 1% Externally Adjustable 0.8V to 5V Output from a 12V Supply Logic-Level PWM Outputs for Interface to External High-Power Drivers Active Current Balancing Between all Phases Built-in Power-Good / Crowbar Functions Programmable Over-Current Protection with Adjustable Latch-Off Delay Description The FAN5182 is a highly efficient, multiphase, synchronous buck switching regulator controller optimized for converting a 12V main supply into a highcurrent, low-voltage supply for use in point-of-load (POL) applications. It uses a multi-loop PWM architecture to drive the logic-level outputs at a programmable switching frequency that can be optimized for regulator size and efficiency. The phase relationship of the output signals can be programmed to provide 1-, 2-, or 3-phase operation, allowing for construction of up to three complementary, interleaved buck switching stages. The FAN5182 provides accurate and reliable overcurrent protection and adjustable current limiting. The FAN5182 is specified over the commercial temperature range of 0C to +85C and is available in a 20-lead Quarter-Size Outline Package (QSOP). Applications Auxiliary Supplies DDR Memory Supplies Point-of-Load Supplies Ordering Information Part Number FAN5182QSCX_NA3E229 Temperature Range 0C to 85C Package QSOP-20L Packing Method Tape and Reel Quantity per Reel 2500 All packages are lead free per JEDEC: J-STD-020B standard. (c) 2005 Fairchild Semiconductor Corporation FAN5182 * Rev. 1.1.3 www.fairchildsemi.com FAN5182 -- Adjustable Output 1-, 2-, or 3-Phase Synchronous Buck Controller Block Diagram Figure 1. Block Diagram (c) 2005 Fairchild Semiconductor Corporation FAN5182 * Rev. 1.1.3 www.fairchildsemi.com 2 FAN5182 -- Adjustable Output 1-, 2-, or 3-Phase Synchronous Buck Controller Pin Assignments Figure 2. Pin Assignments Pin Definitions Pin # 1 2 3 4 5 6 7 8 9 Name VCC FBRTN FB COMP PWRGD EN DELAY RT RAMPADJ Supply Voltage for the Device. Description Feedback Return. Voltage error amplifier reference for remote sensing of the output voltage. Feedback Input. Error amplifier input for remote sensing of the output voltage. An external resistor divider between the output and FBRTN connected to this pin sets the output voltage. This pin is also the reference point for the power-good and crowbar comparators. Error Amplifier Output and Compensation Pin. Power Good Output. Open-drain output that signals when the output voltage is outside the proper operating range. Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the PWRGD output low. Soft-Start Delay and Current Limit Latch-Off Delay Setting Input. An external resistor and capacitor connected between this pin and GND sets the soft-start ramp-up time and the overcurrent latch-off delay time. Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the oscillator frequency of the device. PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal PWM ramp. Current-Limit Set point / Enable Output. An external resistor connected from this pin to GND sets the current limit threshold of the converter. This pin is actively pulled low when the EN input is low, or when VCC is below its UVLO threshold, to signal to the driver IC that the driver high-side and low-side outputs should go low. Current-Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current-sense amplifier. Connect this pin to the common point of the output inductors. Current-Sense Summing Node. External resistors from each switch node to this pin sum the average inductor currents to measure the total output current. Current-Sense Compensation Point. A resistor and a capacitor from this pin to CSSUM determine the gain of the current sense amplifier. Ground. All internal biasing and logic output signals are referenced to this ground. Current Balance Inputs. These are inputs for measuring the current level in each phase. The SW pins of unused phases should be connected to ground. Logic-Level PWM Outputs. Each output is connected to the input of an external MOSFET driver, such as the FAN5109. Connecting the PWM3 output to GND causes that phase to turn off, allowing the FAN5182 to operate as a 1- or 2-phase controller. Do not connect PWM2 to ground for 1-phase operation. 10 ILIMIT 11 12 13 14 CSREF CSSUM CSCOMP GND 15-17 SW3 - SW1 PWM3 PWM1 18-20 (c) 2005 Fairchild Semiconductor Corporation FAN5182 * Rev. 1.1.3 www.fairchildsemi.com 3 FAN5182 -- Adjustable Output 1-, 2-, or 3-Phase Synchronous Buck Controller Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Unless otherwise noted, all voltages are referenced to GND. Symbol VCC FBRTN VCC Parameter Min. -0.3 -0.3 -0.3 -5 -0.3 0 -65 Max. +15 +0.3 5.5 +25 VCC + 0.3 +125 +150 +300 +260 38 90 Unit V V V V V C C C C C/W C/W EN, DELAY, ILIMIT, RT, PWM1-PWM3, COMP SW1-SW3 All Other Inputs and Outputs TJ TSTG TL TLI JC JA Operating Junction Temperature Storage Temperature Lead Soldering Temperature (10 Seconds) Lead Infrared Temperature (15 Seconds) Thermal Resistance Junction-to-Case Thermal Resistance Junction-to-Ambient (1) Note: 1. Junction-to-ambient thermal resistance, JA, is a strong function of PCB material, board thickness, thickness and number of copper planes, number of via used, diameter of via used, available copper surface, and attached heat sink characteristics. It is measured with the device mounted on a board of FR-4 material, 0.063inch thickness, no copper plane, and zero air flow. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol VCC TA Parameter Supply Voltage Range Operating Ambient Temperature Min. 10.8 0 Typ. 12.0 Max. 13.2 +85 Unit V C (c) 2005 Fairchild Semiconductor Corporation FAN5182 * Rev. 1.1.3 www.fairchildsemi.com 4 FAN5182 -- Adjustable Output 1-, 2-, or 3-Phase Synchronous Buck Controller Electrical Characteristics VCC = 12V, FBRTN = GND, * indicates specifications over operating ambient temperature range. (2) Symbol Oscillator fOSC TPHASE VRT VRAMPADJ IRAMPADJ VOL VOH VFB IFB VFB IFBRTN IO(ERR) GBW(ERR) Parameter Frequency Range Conditions * RT = 332k, 3-phase * * * * TA = 25C, RT = 154k, 3-phase RT = 100k to GND RAMPADJ - FB - 2K x IRAMPADJ (with IRAMPADJ set to 20A) (3) Min. 0.25 155 155 155 Typ. Max. 3.00 Units MHz kHz V 200 400 600 2.0 245 245 245 Frequency Variation Output Voltage RAMPADJ Output Voltage RAMPADJ Input Current Range Output Voltage Low Output Voltage High TA = 25C, RT = 100k, 3-phase * -50 0 +50 100 0.3 mV A V V mV A % A A dB MHz V/s Voltage Error Amplifier 3.1 1% * * * FB forced to VOUT - 3% (3) Accuracy (Referenced to FBRTN) FAN5182_NA3E229 Input Bias Current Line Regulation FBRTN Current Output Current DC Gain (3) 792 -4 800 1 0.05 100 500 87 20 10 808 +4 140 FB = 800mV VCC = 10V to 14V Gain Bandwidth Product Slew Rate (3) COMP = FB CCOMP = 10pF CSSUM-CSREF (See Figure 3) * * -5.5 -50 Current-Sense Amplifier VOS(CSA) Offset Voltage DC Gain GBW(CSA) (3) (3) +5.5 +50 70 10 mV nA dB MHz V/s IBIAS(CSSUM) Input Bias Current Gain Bandwidth Product Slew Rate VOL VOH ICSCOMP VSW(X)CM Rsw(X) ISW(X) ISW(X) VOS Match (3) CCSCOMP = 10pF CSSUM & CSREF 0 VCC-2.5 10 VCC-2.5 0.1 500 Input Common-Mode Range Output Voltage Low Output Voltage High Output Current Common-Mode Range Input Resistance Input Current Input Current Matching Offset Voltage Matching (Difference between phases) (3) V V V A Current-Balance Circuit -600 SW(X) = 0V SW(X) = 0V SW(X) = 0V FAN5182_NA3E229 * * * 20 4 -7 30 7 +200 40 10 +7 8 mV k A % mV (c) 2005 Fairchild Semiconductor Corporation FAN5182 * Rev. 1.1.3 www.fairchildsemi.com 5 FAN5182 -- Adjustable Output 1-, 2-, or 3-Phase Synchronous Buck Controller Electrical Characteristics (Continued) VCC = 12V, FBRTN = GND, * indicates specifications over operating ambient temperature range. (2) Symbol VILIMIT(NM) VILIMIT(SD) IILIMIT(NM) VCL Parameter Output Voltage: Normal Mode Output Voltage: In Shutdown Output Current: Normal Mode Maximum Output Current Current Limit Threshold Current Limit Setting Ratio Conditions EN > 2.0V, RILIMIT = 250k EN < 0.8V, IILIMIT = -100A EN > 2.0V, RILIMIT = 250k * VCSREF - VCSCOMP , RILIMIT = 250k VCL/IILIMIT RDELAY = 250k RDELAY = 250k RDELAY = 250k, CDELAY = 12nF During Start-up Delay < 2.4V RDELAY = 250k, CDELAY = 12nF * * * Relative to FBRTN Relative to FBRTN IPWRGD(SINK) = 4mA Relative to FBRTN Relative to FBRTN Over-voltage to PWM Going Low IPWM(SINK) = 400A IPWM(SOURCE) = -400A * * * VCC rising * * * * * * * * * * Min. 2.9 Typ. Max. Units 3.0 12 3.1 400 V mV A A 125 10.4 3.0 1.8 1.5 145 3.1 1.9 mV mV/A V V ms 25 A s 0.8 V V 100 mV +1 660 940 225 200 720 1000 400 A mV mV mV ns V mV ns 500 mV V 10 7.3 1.1 mA V V 750 Current-Limit Comparator 60 105 2.9 1.7 VDELAY(NM) Delay Normal Mode Voltage VDELAY(OC) Delay Over-Current Threshold tDELAY Soft-Start IDELAY(SS) tDELAY(SS) VIL(EN) VIH(EN) IIN(EN) Output Current, Soft-Start Mode Soft-Start Delay Time Input Low Voltage Input High Voltage Input Hysteresis Voltage Input Current (3) Latch-Off Delay Time (3) 15 20 500 Enable Input 2.0 -1 600 880 Power-Good Comparator VPWRGD(UV) Under-Voltage Threshold VPWRGD(OV) Over-Voltage Threshold VOL(PWRGD) Output Low Voltage Power-Good Delay Time VCROWBAR tCROWBAR VOL(PWM) VOH(PWM) Supply DC Supply Current VUVLO UVLO Threshold Voltage UVLO Hysteresis 5 6.5 0.7 6.9 0.9 Crowbar Trip Point Crowbar Reset Point Crowbar Delay Point Output Low Voltage Output High Voltage (3) 0.970 550 1.050 1.105 650 400 160 PWM Outputs 4.0 5 Notes: 2. Limits at operating temperature extremes are guaranteed by design, characterization, and statistical quality control. 3. Guaranteed by design, not tested in production. (c) 2005 Fairchild Semiconductor Corporation FAN5182 * Rev. 1.1.3 www.fairchildsemi.com 6 FAN5182 -- Adjustable Output 1-, 2-, or 3-Phase Synchronous Buck Controller Test Circuit Figure 3. Current-Sense Amplifier Typical Performance Characteristics Figure 4. Master Clock Frequency vs. RT Figure 5. Normalized VFB vs. Temperature Figure 6. Supply Current vs. Oscillator Frequency (c) 2005 Fairchild Semiconductor Corporation FAN5182 * Rev. 1.1.3 www.fairchildsemi.com 7 FAN5182 -- Adjustable Output 1-, 2-, or 3-Phase Synchronous Buck Controller Typical Application Circuit Figure 7. 1.8V, 55A Application Circuit (c) 2005 Fairchild Semiconductor Corporation FAN5182 * Rev. 1.1.3 www.fairchildsemi.com 8 FAN5182 -- Adjustable Output 1-, 2-, or 3-Phase Synchronous Buck Controller Theory of Operation The FAN5182 combines a multi-loop, fixed-frequency PWM control with multi-phase logic outputs for use in 1-, 2-, and 3-phase synchronous buck point-of-load power supplies. Multi-phase operation is important for producing the high current and low voltage demanded by auxiliary supplies in desktop computers, workstations, and servers. Handling high current in a single-phase converter places high thermal stress on components, such as inductors and MOSFETs, and is not preferred. The multi-loop control of the FAN5182 ensures a stable, high-performance topology for: Balancing current and thermal between/among phases Fast response at the lowest possible switching frequency and output decoupling Reducing switching losses due to low-frequency operation Tight line and load regulation Reducing output ripple due to multiphase cancellation Better noise immunity to facilitate PCB layout Master Clock Frequency The clock frequency is set by an external resistor connected from the RT pin to ground. The frequency / resistor relationship follows the graph in Figure 4. To determine the frequency per phase, divide the clock frequency by the number of phases in use. NOTE: The exception is single-phase operation, in which the clock frequency must be set twice the singlephase frequency required. Output Voltage Differential Sensing The FAN5182 uses a differential low-offset voltage error amplifier to maintain 2% differential sensing accuracy over temperature. The output voltage is sensed between the FB and FBRTN pins. The power supply output connects to the FB pin through a resistor divider and the FBRTN pin should be connected directly to the remote sense ground. The internal precision reference is referenced to FBRTN, which has a typical current of 100A to allow accurate remote sensing. The internal error amplifier compares the precision reference to the FB pin to regulate the output voltage. Output Current Sensing The FAN5182 uses a current sense amplifier (CSA) to monitor the total output current for current-limit detection. Sensing the load current at the output gives the total average current being delivered to the load, which is an inherently more accurate method than peak current detection or sampling the current across a sense element, such as the low-side MOSFET. This amplifier can be configured according to the objectives of the system design: Output inductor DCR sensing without a thermistor (for lowest cost) Output inductor DCR sensing with a thermistor (for improved accuracy and moderate cost) Discrete resistor sensing (for best accuracy) The positive input of the CSA is connected to the CSREF pin and the CSREF is tied to the power supply output. The inverting input of the CSA, CSSUM, is the summing node of the load current sense through sensing elements (such as the switch node side of the output inductors). The feedback resistor between CSCOMP and CSSUM sets the gain of the amplifier and a filter capacitor is placed in parallel with this resistor. The gain of the amplifier is programmable by adjusting the feedback resistor. The current information is given as the difference between CSREF and CSCOMP. This "difference" signal is used as a differential input for the current limit comparator. To provide the best accuracy for sensing current, the CSA is designed to have low-input offset voltage. The CSA gain is determined by external resistors, so it can be set very accurately. Start-up Sequence During start-up, the number of operational phases and their phase relationship are determined by the internal circuitry that monitors the PWM outputs. Normally, the FAN5182 operates as a 3-phase PWM controller. Grounding the PWM3 pin programs the FAN5182 for 1or 2-phase operation. When the FAN5182 is enabled, the controller outputs a voltage on PWM3, which is approximately 675mV. An internal comparator checks this pin's voltage versus a threshold of 300mV. If the PWM3 pin is grounded, it is below the threshold and the phase 3 is disabled. The output resistance of the PWM pin is approximately 5k during this detection period. Any external pull-down resistance connected to the PWM pin should not be less than 25k to ensure proper operation. PWM1 and PWM2 are disabled during the phase-detection interval, which occurs during the first two clock cycles of the internal oscillator. After this time, if the PWM3 output is not grounded, the 5k resistance is disconnected, and PWM3 switches between 0V and 5V. If the PWM3 output is grounded, the controller operates in 1- and/or 2-phase. The PWM outputs logic-level signals to interface with external gate drivers, such as the FAN5109. Since each phase is able to operate close to 100% duty cycle, more than one PWM output can be on at the same time. (c) 2005 Fairchild Semiconductor Corporation FAN5182 * Rev. 1.1.3 www.fairchildsemi.com 9 FAN5182 -- Adjustable Output 1-, 2-, or 3-Phase Synchronous Buck Controller Current Control Loop and Thermal Balance The FAN5182 adopts low-side MOSFET RDSON sensing for phase-current balance. The sensed individual phase current is combined with a fixed internal ramp, then compared with the common voltage error amplifier output to balance phase current. This current-balance information is independent of the average output current information used for the current limit. The magnitude of the internal ramp can be set to optimize transient response of the system. It also tracks the supply voltage for better line regulation and transient response. A resistor connected from the power supply input to the RAMPADJ pin determines the slope of the internal PWM ramp. Resistors RSW1 through RSW3 (see Figure 7) can be used to adjust phase current balance. Putting placeholders for these resistors during the initial PCB layout allows phasecurrent balance fine adjustments on the bench if necessary. To increase the current in any given phase, increase RSW for that phase (make RSW = 0 for the hottest phase as the starting point). Increasing RSW to 500 could typically make a substantial increase in this particular phase current. Increase each RSW value by small amounts to optimize phase-current balance, starting with the coolest phase. Figure 8. Typical Start-Up Waveforms Current-Limit and Latch-off Protection The FAN5182 compares a programmable current-limit set point to the voltage from the output of the currentsense amplifier. The level of current limit is set with the resistor from the ILIMIT pin to ground. During normal operation, the voltage on ILIMIT is 3V. The current through the external resistor is internally scaled to give a current-limit threshold of 10.4mV/A. If the difference in voltage between CSREF and CSCOMP rises above the current-limit threshold, the internal current-limit amplifier controls the COMP voltage to maintain the power supply output current at the over-current level. After the limit is reached, the 3V pull-up voltage source on the DELAY pin is disconnected and the external delay capacitor discharges through the external resistor. A comparator monitors the DELAY pin voltage and shuts off the controller when the voltage drops below 1.8V. The current-limit latch-off delay time is therefore set by the RC time constant discharging the delay voltage from 3V to 1.8V. Typical over-current latch-off waveforms are shown in Figure 9. The controller continues to switch all phases during the latch-off delay. If the over-current condition is removed before the 1.8V delay threshold is reached, the controller resumes normal operation. The over-current recovery characteristic also depends on the state of PWRGD. If the output voltage is within the PWRGD window during over current, the controller resumes normal operation once the over-current condition is removed. If overcurrent causes the output voltage to drop below the PWRGD threshold, a soft-start cycle is initiated. Voltage Control Loop A high gain bandwidth voltage error amplifier is used for the voltage control loop. The non-inverting input of the error amplifier is derived from the internal 800mV reference. The output of the error amplifier, the COMP pin sets the termination voltage for the internal PWM ramps plus sensed phase current. The inverting input (FB) is tied to the center point of a resistor divider from the output voltage sense point. Closed-loop compensation is realized via compensator networks connecting to the FB and COMP pins. Soft-Start The soft-start rise time of the output voltage is set by a parallel capacitor and resistor between the DELAY pin and ground. The resistor capacitor (RC) time constant also determines the current-limit latch-off delay time, as explained in the following section. In UVLO or when EN is logic low, the DELAY pin is held to ground. After the UVLO threshold is reached and EN is in logic high state, the delay capacitor is charged with an internal 20A current source. The output voltage follows the ramping voltage on the DELAY pin to limit the inrush current. The soft-start time depends on the value of CDLY with a secondary effect from RDLY. If either EN is logic low or VCC drops below UVLO, the delay capacitor resets to ground and is ready for another soft-start cycle. Figure 8 shows typical start-up waveforms for a softstart sequence. (c) 2005 Fairchild Semiconductor Corporation FAN5182 * Rev. 1.1.3 10 Figure 9. Over-Current Latch-Off Waveforms www.fairchildsemi.com FAN5182 -- Adjustable Output 1-, 2-, or 3-Phase Synchronous Buck Controller The latch-off function can be reset by removing and reapplying VCC or by pulling the EN pin low briefly. To disable the over-current latch-off function, the external resistor connecting the DELAY pin and ground should be removed and a high-value resistor (>1M) should be connected from the DELAY pin to VCC. This prevents the delay capacitor from discharging, so the 1.8V threshold can never be reached. This pull-up resistor has some impact to the soft-start time because the current through this resistor adds additional current to the internal 20A soft-start current. During start-up, when the output voltage is below 200mV, a secondary current limit is activated. This is necessary because the voltage swing of CSCOMP cannot go below ground. This secondary current limit clamps the COMP voltage to 2V. An inherent, per-phase current limit protects individual phases if one or more phases cease to function because of a faulty component. This limit is based on the maximum normal mode COMP voltage. Enable and UVLO To begin switching, the input supply (VCC) to the controller must be higher than the UVLO threshold, and the EN pin must be higher than its logic threshold. If UVLO is less than the threshold or the EN pin is logic low, the FAN5182 is disabled. This holds the PWM outputs at ground, shorts the delay capacitor to ground, and holds the ILIMIT pin at ground. In the application circuit, the ILIMIT pin should be connected to the OD pins of the FAN5109 drivers. Grounding the ILIMIT pin disables the drivers such that both HDRV and LDRV hold low. This feature is important in preventing fast discharge of the output capacitors when the controller shuts off. If the driver outputs are not disabled, a negative output voltage can be generated due to high current discharged from the output capacitors through the inductors. FAN5182 in Single-Phase Applications NOTE: When the FAN5182 is configured for singlephase applications, it is actually operating internally as a two-phase controller. It therefore should be configured as a two-phase controller with only one phase populated externally. To accomplish this, PWM3 needs be grounded (to configure the FAN5182 as a two-phase controller) and the clock frequency set to two times the required phase switching frequency. PWM1 should be used to drive the external phase electronics (driver and MOSFETs). The SW2 and SW3 pins should be connected to ground to minimize any potential spurious noise paths. WARNING: Do not connect PWM2 to ground. As noted above, when using the FAN5182 in singlephase applications, it is actually operating internally as a two-phase controller and PWM2 may be switching. Power-Good Monitoring The power-good comparator monitors the output voltage via the FB pin. The PWRGD pin is an opendrain output whose high level (when connected to a pull-up resistor) indicates that the output voltage is within the nominal limits specified in the Electrical Characteristic table. PWRGD goes low if the output voltage is outside the specified range or whenever the EN pin is pulled low. Figure 10 shows the PWRGD response when the input power supply is switched off. FAN5182 as a Voltage-Mode Controller The SW pins are used to measure the current flowing through the bottom FET. This current information is used to balance the phase currents in a multiphase application and create an inner current-feedback loop in the control loop, making the FAN5182 a current-mode controller. In single-phase applications where phase current balance is not required, the current loop can be defeated by disconnecting the SW pins from the output FETs and shorting the SW pin to ground. This changes the control loop from current-mode control to voltagemode control. WARNING: The compensation requirements for a voltage-mode control design differ for current-mode control design. The Application Information section of this datasheet is for a current-mode control design. The compensation section "Closed-Loop Compensation Design" does not apply to voltage-mode designs. Figure 10. Shutdown Waveforms As part of the protection for the load and output components of the supply, the PWM outputs are driven low (turning on the low-side MOSFETs) when the output voltage exceeds the crowbar trip point. This crowbar action stops once the output voltage falls below the reset threshold of approximately 650mV. Turning on the low-side MOSFETs pulls down the output as the reverse current builds up in the inductors. If the output over-voltage is due to a short in the highside MOSFET, this crowbar action can trip the input supply over-current protection or blow the input fuse, protecting the load from damage. (c) 2005 Fairchild Semiconductor Corporation FAN5182 * Rev. 1.1.3 11 www.fairchildsemi.com FAN5182 -- Adjustable Output 1-, 2-, or 3-Phase Synchronous Buck Controller Application Information Design parameters for a typical high-current DC/DC buck converter, as shown in Figure 7, follow. This is a multiphase, current-mode control implementation. The equations shown are interdependent and must be followed in the sequence shown. For other implementations, adjust the design requirements. NOTE: A complete MathCAD control design program is available from Fairchild upon request. (R) sinks part of the current source to ground. As long as RDLY is greater than 200k, this effect is minor. The value for CDLY can be approximated using: VREF tSS CDLY = 20 A - x 2 x RDLY VREF (2) Design Requirements: Input voltage (VIN) = 12V Output voltage (VOUT) = 1.8V Duty cycle (D) = 0.15 Output current IO = 55A Maximum output current (ILIM) = 110A Number of phases (n) = 3 Switching frequency per phase (fSW ) = 250kHz where tSS is the desired soft-start time. Assuming an RDLY of 390k and a desired soft-start time of 3ms, CDLY is 71nF. The closest standard value for CDLY is 68nF. Once CDLY is chosen, RDLY can be calculated for the current-limit latch-off time, using: RDLY = 1.96 x t DELAY CDLY (3) If the result for RDLY is less than 200k, a smaller softstart time should be considered, by recalculating the equation for CDLY, or a longer latch-off time should be used. RDLY should never be less than 200k. In this example, a delay time of 9ms results in RDLY = 259k. The closest standard 1% value is 261k. Setting the Clock Frequency The FAN5182 uses fixed-frequency control architecture. The frequency is set by an external timing resistor (RT). The clock frequency and the number of phases determine the switching frequency per phase, which relates directly to switching losses and the sizes of the inductors and the input and output capacitors. With n = 3 for three phases, a clock frequency of 750kHz sets the switching frequency, fSW , of each phase to 250kHz, which represents a practical trade-off between the switching losses and the sizes of the output filter components. Equation 1 shows that to achieve a 750kHz oscillator frequency, the correct value for RT is 255k. Alternatively, the value for RT can be calculated using: RT = 1 - 27K n x fSW x 4.7pF 1 - 27K = 256K RT = 3 x 250kHz x 4.7pF Inductor Selection The inductance determines the ripple current in the inductor. Small inductance leads to high ripple current, which increases the output ripple voltage and conduction losses in the MOSFETs and vice versa. In any multiphase converter, it's recommended to design the peak-to-peak inductor ripple current to be less than 50% of the maximum inductor DC current. Equation 4 shows the relationship among the inductance, oscillator frequency, and peak-to-peak ripple current: IR = VOUT x (1 - D) fSW x L (4) Equation 5 can be used to determine the minimum inductance based on a given output ripple voltage: L VOUT x Rx x (1 - (n x D)) fSW x VRIPPLE (1) (5) where RX is the ESR of output bulk capacitors. Solving Equation 5 for a 20mV peak-to-peak output ripple voltage and 3m RX yields: L 1.8 V x 0.7m x (1 - (3 x 0.15)) = 277nH 250kHz x 10mV where 4.7pF and 27k are internal IC component values. For good initial accuracy and frequency stability, a 1% resistor is recommended. The closest standard 1% value for this design is 255k. NOTE: For a single-phase application, set the oscillator frequency to two times the required per-phase switching frequency. This can be done buy substituting "2 x fSW " for "fSW " in Equation 1. (6) Soft-Start and Current-Limit Latch-off Delay Time Because the soft-start and current-limit latch-off delay functions share the DELAY pin, these two parameters must be considered together. The first step is to set CDLY for the soft-start ramp. This ramp is generated with a 20A internal current source. The value of RDLY has a second-order impact on the soft-start time because it (c) 2005 Fairchild Semiconductor Corporation FAN5182 * Rev. 1.1.3 12 If the resulting ripple voltage is too low, the inductance can be reduced until the desired ripple voltage is achieved. In this example, a 600nH inductor is a good starting point that produces a calculated ripple current of 6.6A. The inductor should not saturate at the peak current of 21.6A and should be able to handle the total power dissipation created by the copper and core loss. Another important factor in the inductor design is the Direct Conversion Receiver (DCR), which is used for measuring the phase current. A large DCR can cause excessive power losses, whereas too small DCR can increases measurement error. For this design, a DCR of 1.4m was chosen. www.fairchildsemi.com FAN5182 -- Adjustable Output 1-, 2-, or 3-Phase Synchronous Buck Controller Designing an Inductor Once the inductance and DCR are known, the next step is to either design an inductor or find a suitable standard inductor if one exists. Inductor design starts with choosing appropriate core material. Some candidate materials that have low core loss at high frequencies are powder cores (e.g. Kool-M(R) from Magnetics, Inc. or from Micrometals) and gapped soft ferrite cores (e.g. 3F3 or 3F4 from Philips). Powdered iron cores have higher core loss and are used for lowcost applications. The best choice for a core geometry is a closed-loop type, such as a potentiometer core, a PQ/U/E core, or a toroid core. Some useful references for magnetics design are: Magnetic Designer Software Intusoft (www.intusoft.com) Designing Magnetic Components for HighFrequency DC-DC Converters, by William T. McLyman, Kg Magnetics, Inc., ISBN 1883107008. RPH( x ) = RL x R CS x ILIM VDRPMAX (9) (10) R PH( x ) = 1.4m x 100k x 110A = 140k 110mV WARNING: The parallel combination of the all the Rph resistors must be greater than 30k to ensure that the current sense amplifier does not saturate. Next, use Equation 8 to solve for CCS: Ccs 320nH 2.28nF 1.4m x 100k (11) Choose the closest standard value that is greater than the result given by Equation 8. This example uses a CCS value of 5.6nF. Output Voltage FAN5182 has an internal FBRTN referred 800mV reference voltage VREF. The output voltage can be set by using a voltage divider consisting of resistors RB1 and RB2: VOUT = (R B1 + R B2 ) x VREF R B1 Selecting a Standard Inductor The following power inductor manufacturers can provide design consultation and deliver power inductors optimized for high-power applications upon request: BI Technologies, 714-447-2345 www.bitechnologies.com (12) Rearranging Equation 12 to solve RB2 and assuming a 1%, 1k resistor for RB1 yields R B2 = R B2 = VOUT - VFB x R B1 VFB 1.8 V - 0.8 V x 1k = 1.25k 0 .8 V (13) Taiyo Yuden (USA), 408-573-4150 www.taiyo-yuden.com Output Current Sense The output current can be measured by summing the voltage across each inductor and passing the signal through a low-pass filter. The CS amplifier is configured with resistors RPH(X) (for summing the voltage), and RCS and CCS (for the low-pass filter). The output current IO is set by the following equations: IO = RPH( x ) R CS x VDRP RL The closest standard 1% resistor value for RB2 is 1.24k. Power MOSFETs For this example, one high-side and one low-side N-channel power MOSFET per phase have been selected. The main selection parameters for power MOSFETs are VGS(TH), QG, CISS, CRSS, and RDS(ON). The minimum gate-drive voltage (the supply voltage to the FAN5109) dictates whether standard threshold or logiclevel threshold MOSFETs can be used. With VGATE ~10V, logic-level threshold MOSFETs (VGS(TH) < 2.5V) are recommended. The maximum output current (IO) determines the RDS(ON) requirement for the low-side (synchronous) MOSFETs. With good current balance among phases, the current in each low-side MOSFET is the output current divided by the total number of the low-side MOSFETs (nSF). Since conduction loss is dominant in low-side MOSFET, the following expression can represent total power dissipation in each synchronous MOSFET in terms of the ripple current per phase (IR) and the total output current (IO): I 2 1 n x IR x PSF = (1 - D) x O + nSF 12 n SF 2 (7) (8) Ccs L RL x R CS where: RL is the DCR of the output inductors, VDRP is the voltage drop from CSCOMP to CSREF. When load current reaches its limit, VDRP is at its maximum (VDRPMAX). VDRPMAX can be in the range of 100mV to 200mV. In this example, it is 110mV. Designers have the flexibility of choosing either RCS or RPH(X). It is recommended to select RCS equal to 100k, and then solve for RPH(X) by rearranging Equation 7 as: x RDS(SF) (14) (c) 2005 Fairchild Semiconductor Corporation FAN5182 * Rev. 1.1.3 www.fairchildsemi.com 13 FAN5182 -- Adjustable Output 1-, 2-, or 3-Phase Synchronous Buck Controller Knowing the maximum output current and the maximum allowed power dissipation, determine the required RDS(ON) for the MOSFET. For example, with D-PAK MOSFETs operating up to ambient temperature of 50C, a safe limit for PSF is around 1W to 1.5W at 120C junction temperature. Therefore, in this example, RDS(SF) (per MOSFET) < 7.5m. This RDS(SF) is typically measured at junction temperature of about 120C. In this example, select a lower-side MOSFET with 4.8m at 120C. WARNING: The RDS of the bottom FET is also used to measure the current flowing in the phase. This is used for current balance and for the current-feedback loop. Using a FET with too low an RDS can result in poor current balance and too large a ramp resistor calculation in Equation 18. Another important consideration for choosing the synchronous MOSFET is the input and feedback capacitance. The ratio of feedback to input capacitance must be small (less than 10% is recommended) to prevent accidentally turning on the synchronous MOSFETs when the switch node goes high. Also, the time to switch the synchronous MOSFETs off should not exceed the non-overlap dead time of the MOSFET driver (40ns typical for the FAN5109). The output impedance of the driver is approximately 2 and the typical MOSFET input gate resistances are about 1 to 2; therefore, the total gate capacitance should be less than 6000pF. In the event there are two MOSFETs in parallel, the input capacitance for each synchronous MOSFET should be limited to 3000pF. The high-side (main) MOSFET power dissipation consists of two elements: conduction and switching losses. The switching loss is related to the main MOSFET's turn-on and turn-off time and the current and voltage being switched. Based on the main MOSFET's switching speed (rise and fall time that the gate driver can offer) and MOSFET input capacitance, the following expression provides the approximate switching loss for each main MOSFET: PS(MF) = 2 x fSW x VCC x IO n x R G x MF x CISS nMF n Typically, for main MOSFETs, a low gate charge (CISS) device is preferred, but low gate charge MOSFETs usually have higher on resistance. Select a device that meets total power dissipation around 1.5W for a single D-PAK MOSFET. In this example, a FDD6296 is selected as the main MOSFET (three total; nMF = 3), with a CISS = 1440pF, and RDS(MF) = 9m (at TJ = 120C). A FDD8896 is selected as the synchronous MOSFET (three total; nSF = 3), with CISS = 2525pF and RDS(SF) = 5.4m (at TJ = 120C). The synchronous MOSFET CISS is less than 6000pF. Solving for the power dissipation per MOSFET at IO = 55A and IR = 6.6A yields 1.56W for each synchronous MOSFET and 1.29W for each main MOSFET. These numbers comply with the power dissipation limit of around 1.5W per MOSFET. One more item that needs to be considered is the power dissipation in the driver for each phase. The gate-drive loss is described in terms of the QG for the MOSFETs and is given by the following equation: f PDRV = SW x (nMF x Q GMF + n SF x QGSF ) + ICC x VCC 2xn (17) where: QGMF is the total gate charge for each main MOSFET, QGSF is the total gate charge for each synchronous MOSFET. ICC x VCC in Equation 17 represents the driver's standby power dissipation. For the FAN5109, the maximum dissipation should be less than 400mW. In this example, with ICC = 5mA, QGMF = 25nC, and QGSF = 50nC; there is 285mW in each driver, which is below the 400mW dissipation limit. See the Thermal Information table in the FAN5109 datasheet for details. Ramp Resistor Selection The ramp resistor (RR) is used for setting the size of the internal PWM ramp. The value of this resistor is chosen to provide the best combination of phase-current balance, stability, and transient response. The following expression is used to determine the optimum value: RR = AR x L 3 x A D x R DS( ON)(SF ) x CR (15) where: nMF is the total number of main MOSFETs; RG is the total gate resistance (2 for the FAN5109 and about 1 for typical logic level N-channel MOSFETs, total RG = 3); CISS is the input capacitance of the main MOSFET. Note that adding more main MOSFETs (nMF) does not help lower the switching loss for each main MOSFET; it can only reduce conduction loss. The most efficient way to reduce switching loss is to use low-gate charge / capacitance devices. The conduction loss of the main MOSFET is given by: PC(MF ) I = D x O nMF 1 n x IR + x 12 nMF 2 (18) (19) RR = 0.2 x 320nH = 356k 3 x 5 x 2.4m x 5pF where: AR is the internal ramp amplifier gain, AD is the current balancing amplifier gain, RDS(ON)(SF) is the equivalent low-side MOSFET on resistance, CR is the internal ramp capacitor value. The closest standard 1% resistor value is 332k. x R DS(MF ) 2 (16) where RDS(MF) is the on resistance of the main MOSFET. (c) 2005 Fairchild Semiconductor Corporation FAN5182 * Rev. 1.1.3 www.fairchildsemi.com 14 FAN5182 -- Adjustable Output 1-, 2-, or 3-Phase Synchronous Buck Controller WARNING: The ramp resistor should be less than 1M to ensure that board contaminates don't affect the ramp. If the calculated value is greater than 1M, verify that the RDS of the bottom FET is not too low. Internal ramp voltage magnitude can be calculated by: VR = A R x (1 - D) x VOUT RR x CR x fSW (20) (21) If RLIM is greater than 500k, the actual current-limit threshold may be lower than the intended value. Some adjustment for RLIM may be needed. Here, ILIM is the average current limit for the output of the supply. In this example, using the VDRPMAX value of 110mV from Equations 7 and 8 and choosing a peak current limit of 110A for ILIM results in RLIM = 284k, for which 287k is chosen as the nearest 1% value. The per-phase current limit is determined by: IPHLIM VCOMP(MAX ) - VR - VBIAS A D x R DS(MAX ) + IR 2 VR = 0.2 x (1 - 0.15) x 1.8V = 686mV 357K x 5pF x 250kHz (24) The size of the internal ramp can be made larger or smaller. If it is made larger, stability and transient response improve, but thermal balance degrades. If the ramp is made smaller, thermal balance improves, but transient response and stability degrade. The factor of three in the denominator of Equation 18 sets a ramp size with optimal balance for good stability, transient response, and thermal balance. Closed-Loop Compensation Design NOTE: This section does not apply in a voltage-mode control configuration. Optimum compensation assures the best possible load regulation and transient response of the regulator. The target of the compensation design is to achieve reasonably high control bandwidth with sufficient phase and gain margin. The power stage of the synchronous buck converter consists of two poles and one zero. A two-pole, onezero compensator of the voltage error amplifier is adequate for proper compensation if the output bulk capacitors are electrolytic types (low ESR zero). Equations 25-27 are able to yield an approximate starting point for the design. To further optimize the design, some bench adjustments may be necessary. Ramp Resistor Selection for Voltage-Mode Control When configured for single-phase voltage-mode control (SW pin grounded), the ramp resistor is selected to produce a fixed-ramp voltage. For example, to create a ramp voltage of 1V, the following equation is used: RR = 0.2 x (VIN - VREF ) x VOUT - 2000 VIN x fSW x C R x d Vr (22) where: RR is the ramp resistor connected between VIN and FAN5182 RAMPADJ pin 9 0.2 is the internal current transfer ratio between RRAMPADJ and the PWM ramp current source(s) VIN is the input voltage (12V) VREF is the internally generated reference (0.8V) VOUT is the output voltage CR is the internal PWM ramp capacitor, 5pF fsw is the switching frequency defined as (Master Osc / 2) for single- and dual-phase operation and (Master Osc / 3) for three-phase operation dVr is the target peak ramp voltage; 1V is a typical target voltage. C x RX n x RX CA = X x RB2 VR x RL + (A D xRDS ) V OUT RA = C FB = (25) L A D x R DS R B2 V x R x - - C X x R X (26) C X x R X VOUT n x R X 2 x fSW x R X 1 2 x n x fSW x R A (27) If CX is 6000F (five 1200F capacitors in parallel) with an equivalent ESR of 3m, the equations above give the following compensation values: CA = 1.33nF, RA= 6.05k, CFB = 110pF (28) Selecting the nearest standard value for each of these components yields: CA = 1.2nF, RA = 6.04k, and CFB = 100pF (29) As mentioned above, this compensation design scheme is typically good for applications using electrolytic type capacitors, where the capacitor ESR zero can roughly cancel one of the power stage poles. However, for all ceramic capacitor types of applications, since the capacitor ESR zero can be very high, a three-pole, twozero compensator should be used. Current Limit Set Point The current-limit threshold is set with a 3V source VLIM across RLIM with a gain of 10.4mV/A (ALIM). RLIM can be found using: R LIM = A LIM x V LIM V DRPMAX (23) WARNING: Be sure to take into account the peak current ripple current and the increase in inductor DCR at high temperatures if the inductor is not temperature compensated. (c) 2005 Fairchild Semiconductor Corporation FAN5182 * Rev. 1.1.3 www.fairchildsemi.com 15 FAN5182 -- Adjustable Output 1-, 2-, or 3-Phase Synchronous Buck Controller Input Capacitor Selection and Input Current di/dt Reduction In continuous inductor current mode, the source current of the high-side MOSFET is approximately a square wave with a duty ratio equal to D x VOUT/VIN and an amplitude equal to the output current. To prevent large voltage variation, a low-ESR input capacitor, sized for the maximum rms current, must be used. The maximum rms capacitor current is given by: ICRMS = D x IO x 1 -1 nxD (30) (31) Figure 11. Temperature Compensation Circuit ICRMS = 0.15 x 55 A x 1 - 1 = 9.1A 3 x 0.15 Note that manufacturers often specify capacitor ripple current rating based on only 2,000 hours of life. Therefore, it is advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. Several capacitors may be placed in parallel to meet size or height requirements in the design. In this example, the input capacitor bank is formed by two 2,700F, 16V aluminum electrolytic capacitors and three 4.7F ceramic capacitors. To reduce the input current di/dt to a level below the system requirement, in this example 0.1A/s, an additional small inductor (L > 370nH at 10A) can be inserted between the converter and the supply bus. This inductor serves as a filter between the converter and the primary power source. WARNING: During start-up with a pre-charged output capacitor the capacitor, is discharged prior to the converter starting. The energy that was stored in the output capacitor is transferred to the input voltage through the upper FET. This can cause a momentary increase in VIN that could exceed the VIN maximum specification for the controller or driver if there is insufficient capacitance on VIN. Follow the procedures and expressions shown below for calculation of RCS1, RCS2, and RTH (the thermistor value at 25C) based on a given RCS value. 1. Select an NTC according to type and value. With no value yet, start with a thermistor with a value close to RCS. The NTC should also have an initial tolerance of better than 5%. 2. Based on the NTC type, find its relative resistance value at two temperatures. The temperatures that work well are 50C and 90C. These resistance values are called A (RTH(50C)/RTH(25C)) and B(RTH(90C)/RTH(25C)). Note that the NTC's relative value is always 1 at 25C. 3. Find the relative value of RCS required for each of these temperatures. This is based on the percentage of change needed, which, in this example, is initially 0.39%/C. These are called r1 (1/ (1 + TC x (T1 - 25))) and r2 (1/ (1 + TC x (T2 25))), where TC = 0.0039 for copper. T1 = 50C and T2 = 90C are chosen. From this, calculate that r1 = 0.9112 and r2 = 0.7978. 4. Compute the relative values for RCS1, RCS2, and RTH using Equations 33, 34, and 35. rCS2 = ( A - B ) x r1 x r2 - A x (1 - B ) x r2 + B x (1 - A ) x r1 A x (1 - B) x r1 - B x (1 - A ) x r2 - ( A - B ) To ensure that this does not happen, use the following equation to calculate a minimum value of CIN: CIN COUT 6 VO VINMax - VINNorm 2 2 (33) (34) rCS1 = (32) rTH Inductor DCR Temperature Correction With the inductor's DCR being used as the sense element, its necessary to compensate for temperature changes in the inductor's winding if an accurate currentlimit set point is desired. Fortunately, copper has a wellknown temperature coefficient (TC) of 0.39%/C. If RCS is designed to have an opposite and equal percentage of change in resistance to that of the inductor wire, it cancels the temperature variation of the inductor's DCR. Due to the nonlinear nature of NTC thermistors, resistors RCS1 and RCS2 are needed. See Figure 11 for instructions on how to linearize the NTC and produce the desired temperature coefficient. (c) 2005 Fairchild Semiconductor Corporation FAN5182 * Rev. 1.1.3 (1 - A ) 1 A - 1- r CS2 r1 - rCS2 1 = 1 1 - 1- r r -r CS 2 1 CS1 (35) 5. Calculate RTH = rTH x RCS, then select the closest thermistor value available. Also, compute a scaling factor k based on the ratio of the actual thermistor value used relative to the computed one: k= R TH( ACTUAL ) R TH(CALCULATED ) (36) 6. Calculate values for RCS1 and RCS2 using: R CS1 = R CS x k x rCS1 R CS 2 = R CS x ((1 - k ) + (k x rCS 2 )) (37) (38) www.fairchildsemi.com 16 FAN5182 -- Adjustable Output 1-, 2-, or 3-Phase Synchronous Buck Controller PCB Layout Guidelines General Recommendations To achieve the best performance, a PCB with at least four layers is recommended. When designing the layout, keep in mind that each square unit of 1-ounce copper has resistance of ~0.53m at room temperature. Whenever high currents must be routed to a different PCB layers, vias should be used properly to create several parallel current paths so the resistance and inductance introduced by these current paths are minimized and via current rating is not exceeded. If critical signal traces must be routed close to power circuitry, a signal ground plane must be interposed between those signal lines and the traces of the power circuitry. This serves as a shield to minimize noise injection into the signals at the expense of making signal ground a bit noisier. An analog ground island should be used around and under the FAN5182 as a reference for the components associated with the controller. The analog ground should be connected to the power ground at a single point. The components around the FAN5182 should be close to the controller with short traces. The output capacitors should be placed as close as possible to the load. If the load is distributed, the capacitors should also be distributed in proportion to the respective load. to minimize the inductance in the MOSFET half bridge. Failure to do so can lead to severe phase node ringing. A snubber circuit is always recommended to partly kill the phase node switching noise. Whenever using a power dissipating component; for example, a power MOSFET that is soldered to the PCB; the proper use of vias, both directly on the mounting pad and immediately surrounding the mounting pad is recommended. Make a mirror image of the power pad being used on the component side to heat sink the MOSFETs on the opposite side of the PCB. Use large copper pour for high-current traces to lower the electrical impedance and help dissipate heat. Do not make the switching node copper pour unnecessarily large, since it could radiate noise. An undisturbed solid power ground plane should be used as one of the inner layers. Signal Circuitry Recommendations The output voltage is sensed from the FB and the FBRTN pins. To avoid differential mode noise pickup in these differential sensed traces, the loop area between the FB and FBRTN traces should be minimized. In other words, the FB and FBRTN traces should be routed adjacent to each other with minimum spacing on top of the analog / power ground plane back to the controller. The signal traces connecting to the switch nodes should be tied as close as possible to the inductor pins. The CSREF sense trace should be connected to the second nearest inductor pin to the controller. Detailed step-by-step PCB layout instructions are available from Fairchild upon request. Power Circuitry Recommendations The PCB layout starts with high-frequency power component placement. Try to minimize stray inductance of the MOSFET half bridge, which is composed of the input capacitors and top and bottom MOSFETs. A good practice is to use short and wide traces or copper pours (c) 2005 Fairchild Semiconductor Corporation FAN5182 * Rev. 1.1.3 www.fairchildsemi.com 17 FAN5182 -- Adjustable Output 1-, 2-, or 3-Phase Synchronous Buck Controller Physical Dimensions Figure 12. 20-Pin Quarter-Size Outline Package (QSOP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ (c) 2005 Fairchild Semiconductor Corporation FAN5182 * Rev. 1.1.3 www.fairchildsemi.com 18 FAN5182 -- Adjustable Output 1-, 2-, or 3-Phase Synchronous Buck Controller (c) 2005 Fairchild Semiconductor Corporation FAN5182 * Rev. 1.1.3 www.fairchildsemi.com 19 |
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